1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for determining a sampling plan based on defectivity.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Generally, a set of processing steps is performed on a lot of wafers using a variety of processing tools, including photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, implantation tools, etc. The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender non-optimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
One technique for improving the operation of a semiconductor processing line includes using a factory wide control system to automatically control the operation of the various processing tools. The manufacturing tools communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface that facilitates communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script based upon a manufacturing model, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. Often, semiconductor devices are staged through multiple manufacturing tools for multiple processes, generating data relating to the quality of the processed semiconductor devices.
Data gathered during the course of wafer processing is used to identify and attempt to mitigate the effects of process and equipment variations by implementing automatic control techniques based on the collected feedback. Current semiconductor processing techniques typically collect meteorology data at a fixed rate (e.g., every fourth lot processed in a tool) or by pre-assigning a fixed percentage of lots for measurement. Because lots are not typically processed in a particular order, the percentage technique sometimes results in periods where multiple lots are measured consecutively, followed by periods where no lots are measured. Such static sampling plans sometimes do not diagnose process or system issues expeditiously. As a result defective wafers could be manufactured, necessitating costly rework or scrapping of the wafers.
Different processes performed during the fabrication of devices, by nature, have different propensities for inducing defects in the processed devices. Typically, one process tool may be used to perform a process using different operating recipes (e.g., different etching recipes for different process layers formed on a wafer). Static sampling plans typically measure a predetermined number of wafers processed in the process tool. Such static sampling plans sometimes fail to provide adequate data for effective process control or fault detection given the different defectivity characteristics of the processes being performed.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method including processing a plurality of workpieces in accordance with an operating recipe. A defectivity metric is determined based on the operating recipe. A sampling plan for measuring a characteristic of selected workpieces processed using the operating recipe is determined based on the defectivity metric.
Another aspect of the present invention is seen in a manufacturing system including a process tool and a sampling controller. The process tool is configured to process a plurality of workpieces in accordance with an operating recipe. The sampling controller is configured to determine a defectivity metric based on the operating recipe and determine a sampling plan for measuring a characteristic of selected workpieces processed using the operating recipe based on the defectivity metric.